1. Field of the Invention
The present invention relates to a manufacturing process of a semiconductor non-volatile memory cell, and to the corresponding memory cell, and more particularly, to the manufacture of a non-volatile memory cell, e.g., of the flash EEPROM type, having an interpoly dielectric layer of reduced electrical thickness, for a given number of interpoly dielectric layers, to ensure proper performance of the device as regards its electrical characteristics and retention of a logic state programmed therein.
The invention further relates to a process for manufacturing, either to a very large integration scale or single wafer scale, flash EEPROM non-volatile memory devices exhibiting the above features.
2. Description of the Related Art
As is well known in this technical field, re-programmable non-volatile memory cells integrated in a semiconductor substrate, particularly flash EEPROM cells, comprise a floating gate FET (Field-Effect Transistor), and an interpoly dielectric layer provided between the floating gate region and the control gate region to function as an insulator layer of charges stored into the floating gate region. The absence or presence of charges in the floating gate region sets the logic state of the memory cell, usually by a binary code of 0 or 1.
The interpoly dielectric layer can be formed from different materials in a number of different ways. A common technique is that of successively depositing three dielectric layers onto the floating gate region, the latter being comprised conventionally of an amorphous or polycrystalline silicon layer (polysilicon layer) deposited onto a thin layer of silicon oxide, known as the tunnel oxide, to isolate the gate region from the semiconductor substrate. The resulting stack dielectric layer usually comprises a first silicon oxide layer, a second silicon nitride layer, and a third silicon oxide layer. The resulting dielectric is known by the ONO acronym (Oxide Nitride Oxide), or as the interpoly ONO dielectric.
Within the ONO layer, the capability of the cell to retain its logic state is provided essentially by the two layers of silicon oxide. The nitride layer is used to promote the integration of the three-stack layer to the device process flow. The interpoly dielectric forming step is followed by treatments with oxidizing species (O2, O, OH, H2O). The nitride layer is impervious to said oxidizing species, and is therefore used as a barrier to stop them from diffusing through to the floating gate region. Thus, the nitride layer prevents further oxidation of the floating gate region and consequent alteration of the interpoly dielectric layer thickness during subsequent device manufacturing steps. In the state of the art, the need to maintain a nitride layer of sufficient thickness to function as a barrier against later thermal treatment, and the need to keep the ONO layer retention properties unchanged, inhibit reducing the overall electrical thickness of the three-stack layer to less than 14 nm. Alternatively, with memory cells that require no particularly thin interpoly dielectric or that are subjected to no post-formation oxidizing treatments, a single silicon oxide layer (single oxide interpoly) may be used instead of the ONO layer.
The thickness of the interpoly dielectric layer is co-responsible, irrespective of its composition and manufacturing method, for the capacitive coupling of the memory cell. Thus, additionally to retaining the logic state over time, it contributes to set the program and erase parameters.
The extant demand for miniaturization of electronic devices and for lower power usage, involving lower device bias voltages, requires that the thickness of the active dielectric layers be reduced at no performance loss.
The underlying technical problem is to provide a memory cell manufacturing process, whereby the EOT (Equivalent Oxide Thickness) of the dielectric layer between the floating gate and control gate regions can be reduced while maintaining the same fisic thickness and achieving good capacitive coupling of the floating and control gate regions.